minicpu - Quartus II Compilation Report File


Report Information
ProjectC:\minagawa\minicpu\db\minicpu.quartus_db
Compiler Settingsminicpu
Quartus II Version1.1 Build 155 07/18/2001


Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "minicpu" Compiler Settings
            Summary
            Compiler Settings
            Hierarchy
            Floorplan View
            Device Options
            Resource Section
                Resource Usage Summary
                Input Pins
                Output Pins
                All Package Pins
                Control Signals
                Global & Other Fast Signals
                Logical Memories
                Carry Chains
                Cascade Chains
                Embedded Cells
                Non-Global High Fan-Out Signals
                Peripheral Signals
                Local Routing Interconnect
                MegaLAB Interconnect
                LAB External Interconnect
                MegaLAB Usage Summary
                Row Interconnect
                LAB Column Interconnect
                ESB Column Interconnect
            Messages
            Equations
            Pin-Out File
            Timing Analyses
                Timing Settings
                fmax (not incl. delays to/from pins)
                Register-to-Register fmax
                tsu (Input Setup Times)
                th (Input Hold Times)
                tco (Clock to Output Delays)
            Processing Time


Legal Notice

Copyright (C) 1991-2001 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein.

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General Settings
Option Setting
Start date & time 03/04/2002 17:27:54
Main task Compilation
Settings name minicpu

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Summary
Processing status Fitting Successful
Timing requirements/analysis status No requirements
Chip name minicpu
Device name EP20K200EFC484-2X
Total logic elements 762 / 8320 ( 9 % )
Total pins 62 / 376 ( 16 % )
Total ESB bits 2048 / 106496 ( 1 % )

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Compiler Settings
Option Setting
Chip name minicpu
Family name APEX20KE
Focus entity name |minicpu
Device EP20K200EFC484-2X
Compilation mode Full
Disk space/compilation speed tradeoff Normal
Preserve fewer node names On
Use timing-driven compilation to optimize internal timing Normal Compilation
Use timing-driven compilation to optimize I/O timing On
Generate timing analyses On

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Hierarchy
CompileHierarchy
   MINICPU
      cu:CU
      eu:EU
         lpm_add_sub:1256
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1260
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1275
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1280
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1281
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1287
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1292
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1293
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1299
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1304
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1308
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
         lpm_add_sub:1312
            addcore:adder
               a_csnbuffer:cout_node
               a_csnbuffer:oflow_node
               a_csnbuffer:result_node
            altshift:carry_ext_latency_ffs
            altshift:oflow_ext_latency_ffs
            altshift:result_ext_latency_ffs
      io:IO
      mu:MU
         ram256x8:ram
            lpm_ram_dq:inst_1
               altram:sram
      ru:RU
      counter8:c1
         SY_JKFF:u0
         SY_JKFF:u1
         SY_JKFF:u2
         SY_JKFF:u3
         SY_JKFF:u4
         SY_JKFF:u5
         SY_JKFF:u6
         SY_JKFF:u7

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Floorplan View
Floorplan report data cannot be output to HTML.
Please use Quartus II to view the floorplan report data.

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Device Options
Option Setting
Auto-restart configuration after error Off
Release clears before tri-states Off
Enable user-supplied start-up clock (CLKUSR) Off
Enable device-wide reset (DEV_CLRn) Off
Enable device-wide output enable (DEV_OE) Off
Enable INIT_DONE output Off
Auto-increment JTAG user code for multiple configuration devices On
Disable CONF_DONE and nSTATUS pull-ups on configuration device Off
Generate Tabular Text File (.ttf) Off
Generate Raw Binary File (.rbf) Off
Generate Hexadecimal Output File (.hexout) Off
Configuration scheme Passive Serial
Hexadecimal Output File count direction Up
JTAG user code for target device 0XFFFFFFFF
JTAG user code for configuration device 0XFFFFFFFF
Hexadecimal Output File start address 0
Reserve all unused pins As output driving ground
Configuration device EPC2LC20
Use check sum as user code Off
Use check sum as user code for EPROM Off

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Resource Usage Summary
Resource Usage
Clock pins 1
Fast i/o pins 0
Global signals 4
I/O pins 61
Logic elements 762
ESBs 1 / 52 ( 1 % )
Macrocells 0
Flipflops 93
FastRow interconnects 0 / 120 ( 0 % )
Maximum fan-out 88
Maximum fan-out node cu:CU|ALUc[4]~reg0
Total fan-out 2713
Average fan-out 3.3
ESB pterm bits used 0 / 106496 ( 0 % )
ESB non-CAM memory bits used 2048 / 106496 ( 1 % )
ESB CAM bits used 0 / 106496 ( 0 % )
Total ESB bits used 2048 / 106496 ( 1 % )

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Input Pins
Name Pin # MegaLAB Row MegaLAB Col. Col. Fan-Out Global I/O Register Use Local Routing Input Power Up High Slow Slew Rate Delay Chain PCI I/O Enabled Single-Pin CE FastRow Interconnect I/O Standard
res Y10 -- 1 14 40 no no no no no yes no no no LVTTL
CLKa L6 -- -- -- 8 yes no no no no no no no no LVTTL

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Output Pins
Name Pin # MegaLAB Row MegaLAB Col. Col. I/O Register Use Local Routing Output Power Up High Slow Slew Rate Delay Chain PCI I/O Enabled Single-Pin OE Single-Pin CE Open Drain I/O Standard
OUT[7] U15 -- 2 6 no no no no no no no no no LVTTL
A[7] Y16 -- 2 7 no no no no no no no no no LVTTL
OUT[6] U16 -- 2 5 no no no no no no no no no LVTTL
A[6] Y22 W -- -- no no no no no no no no no LVTTL
A[5] R13 -- 2 9 no no no no no no no no no LVTTL
OUT[5] AA20 W -- -- no no no no no no no no no LVTTL
B[7] T21 Q -- -- no no no no no no no no no LVTTL
WR T19 T -- -- no no no no no no no no no LVTTL
B[5] P19 P -- -- no no no no no no no no no LVTTL
B[4] R18 S -- -- no no no no no no no no no LVTTL
B[3] T20 Q -- -- no no no no no no no no no LVTTL
B[6] P17 S -- -- no no no no no no no no no LVTTL
B[1] U20 T -- -- no no no no no no no no no LVTTL
B[0] W20 S -- -- no no no no no no no no no LVTTL
B[2] K18 N -- -- no no no no no no no no no LVTTL
RD AB18 Y -- -- no no no no no no no no no LVTTL
OUT[4] W18 -- 2 1 no no no no no no no no no LVTTL
A[4] P18 R -- -- no no no no no no no no no LVTTL
ZF W16 -- 2 6 no no no no no no no no no LVTTL
ACC[7] P2 S -- -- no no no no no no no no no LVTTL
state[5] AB21 X -- -- no no no no no no no no no LVTTL
state[6] L16 O -- -- no no no no no no no no no LVTTL
state[7] Y14 -- 2 12 no no no no no no no no no LVTTL
state[2] M20 O -- -- no yes no no no no no no no LVTTL
state[0] L15 P -- -- no no no no no no no no no LVTTL
state[4] L17 O -- -- no no no no no no no no no LVTTL
state[1] U19 T -- -- no no no no no no no no no LVTTL
state[3] L20 N -- -- no no no no no no no no no LVTTL
IR[6] J18 N -- -- no no no no no no no no no LVTTL
IR[7] AA18 X -- -- no no no no no no no no no LVTTL
IR[5] AA13 Z -- -- no no no no no no no no no LVTTL
IR[4] V17 -- 2 4 no no no no no no no no no LVTTL
IR[0] Y12 -- 2 15 no no no no no no no no no LVTTL
IR[2] L14 Q -- -- no no no no no no no no no LVTTL
IR[1] N18 O -- -- no no no no no no no no no LVTTL
IR[3] AB20 X -- -- no no no no no no no no no LVTTL
MARl V19 T -- -- no no no no no no no no no LVTTL
OUT[3] U18 -- 2 3 no no no no no no no no no LVTTL
A[3] V13 -- 2 14 no no no no no no no no no LVTTL
ACC[6] R2 S -- -- no no no no no no no no no LVTTL
OUT[1] P16 U -- -- no no no no no no no no no LVTTL
A[1] Y18 -- 2 2 no no no no no no no no no LVTTL
OUT[0] W17 -- 2 4 no no no no no no no no no LVTTL
A[0] AA19 W -- -- no no no no no no no no no LVTTL
OUT[2] W15 -- 2 8 no no no no no no no no no LVTTL
A[2] W19 V -- -- no no no no no no no no no LVTTL
C[1] Y13 -- 2 13 no no no no no no no no no LVTTL
C[0] U21 S -- -- no no no no no no no no no LVTTL
C[5] W21 V -- -- no no no no no no no no no LVTTL
C[2] N17 Q -- -- no no no no no no no no no LVTTL
C[3] AA17 X -- -- no no no no no no no no no LVTTL
C[4] Y20 U -- -- no no no no no no no no no LVTTL
ACC[0] K2 R -- -- no no no no no no no no no LVTTL
C[7] R1 S -- -- no no no no no no no no no LVTTL
C[6] N15 S -- -- no no no no no no no no no LVTTL
ACC[5] T1 S -- -- no no no no no no no no no LVTTL
ACC[1] R19 R -- -- no no no no no no no no no LVTTL
ACC[2] N16 R -- -- no no no no no no no no no LVTTL
ACC[4] U3 S -- -- no no no no no no no no no LVTTL
ACC[3] U22 R -- -- no no no no no no no no no LVTTL

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All Package Pins
Pin # Usage I/O Standard
A1 GND  
A2 GND*  
A3 GND*  
A4 GND*  
A5 GND*  
A6 GND*  
A7 GND*  
A8 GND*  
A9 N.C.  
A10 N.C.  
A11 GND  
A12 N.C.  
A13 N.C.  
A14 N.C.  
A15 GND*  
A16 GND*  
A17 GND*  
A18 GND*  
A19 GND*  
A20 GND*  
A21 GND*  
A22 GND  
B1 VCCINT  
B2 GND  
B3 GND*  
B4 GND*  
B5 GND*  
B6 GND*  
B7 GND*  
B8 GND*  
B9 GND*  
B10 GND*  
B11 GND*  
B12 GND*  
B13 GND*  
B14 GND*  
B15 GND*  
B16 GND*  
B17 GND*  
B18 GND*  
B19 GND*  
B20 GND*  
B21 GND  
B22 VCCINT  
C1 GND*  
C2 GND*  
C3 GND*  
C4 GND*  
C5 GND*  
C6 GND*  
C7 GND*  
C8 GND*  
C9 GND*  
C10 GND*  
C11 GND*  
C12 GND*  
C13 GND*  
C14 GND*  
C15 GND*  
C16 GND*  
C17 GND*  
C18 GND*  
C19 GND*  
C20 GND*  
C21 GND*  
C22 GND*  
D1 GND*  
D2 GND*  
D3 GND*  
D4 GND*  
D5 GND*  
D6 GND*  
D7 GND*  
D8 GND*  
D9 GND*  
D10 GND*  
D11 GND+  
D12 #TRST  
D13 GND*  
D14 GND*  
D15 GND*  
D16 GND*  
D17 GND*  
D18 GND*  
D19 GND*  
D20 GND*  
D21 GND*  
D22 GND*  
E1 GND*  
E2 GND*  
E3 GND*  
E4 GND*  
E5 GND*  
E6 GND*  
E7 GND*  
E8 GND*  
E9 GND*  
E10 GND*  
E11 #TDO  
E12 ^nCEO  
E13 GND*  
E14 GND*  
E15 GND*  
E16 GND*  
E17 GND*  
E18 GND*  
E19 GND*  
E20 GND*  
E21 GND*  
E22 GND*  
F1 GND*  
F2 GND*  
F3 GND*  
F4 GND*  
F5 GND*  
F6 GND  
F7 GND*  
F8 GND*  
F9 GND*  
F10 GND*  
F11 GND*  
F12 GND+  
F13 GND*  
F14 GND*  
F15 GND*  
F16 GND*  
F17 GND  
F18 GND*  
F19 GND*  
F20 GND*  
F21 GND*  
F22 GND*  
G1 GND*  
G2 GND*  
G3 GND*  
G4 GND*  
G5 GND*  
G6 GND*  
G7 GND  
G8 VCCIO  
G9 GND*  
G10 GND*  
G11 GND*  
G12 GND*  
G13 GND*  
G14 GND*  
G15 GND*  
G16 GND  
G17 GND*  
G18 GND*  
G19 GND*  
G20 GND*  
G21 GND*  
G22 GND*  
H1 GND*  
H2 GND*  
H3 GND*  
H4 GND*  
H5 GND*  
H6 GND*  
H7 VCCIO  
H8 GND  
H9 VCCINT  
H10 GND*  
H11 GND*  
H12 GND*  
H13 GND*  
H14 VCCIO  
H15 GND  
H16 GND*  
H17 GND*  
H18 GND*  
H19 GND*  
H20 GND*  
H21 GND*  
H22 GND*  
J1 GND*  
J2 GND*  
J3 GND*  
J4 GND*  
J5 GND*  
J6 GND*  
J7 GND*  
J8 VCCINT  
J9 GND  
J10 VCCIO  
J11 GND  
J12 GND*  
J13 VCCINT  
J14 GND  
J15 VCCIO  
J16 GND*  
J17 GND*  
J18 IR[6] LVTTL
J19 GND*  
J20 GND*  
J21 GND*  
J22 GND*  
K1 GND*  
K2 ACC[0] LVTTL
K3 GND*  
K4 GND*  
K5 GND*  
K6 GND*  
K7 GND*  
K8 GND*  
K9 VCCIO  
K10 GND  
K11 VCCINT  
K12 VCCIO  
K13 GND  
K14 VCCINT  
K15 GND*  
K16 GND*  
K17 GND+  
K18 B[2] LVTTL
K19 GND*  
K20 GND*  
K21 GND*  
K22 GND*  
L1 VCCIO  
L2 GND  
L3 GND*  
L4 ^DATA0  
L5 ^DCLK  
L6 CLKa LVTTL
L7 GND*  
L8 GND*  
L9 VCC_CKLK  
L10 VCCINT  
L11 GND  
L12 GND  
L13 VCCIO  
L14 IR[2] LVTTL
L15 state[0] LVTTL
L16 state[6] LVTTL
L17 state[4] LVTTL
L18 ^MSEL1  
L19 ^MSEL0  
L20 state[3] LVTTL
L21 GND*  
L22 VCCIO  
M1 GND  
M2 GND*  
M3 GND*  
M4 ^nCE  
M5 #TDI  
M6 GND*  
M7 GND*  
M8 VCC_CKLK  
M9 GND_CKLK  
M10 VCCIO  
M11 GND  
M12 GND  
M13 VCCINT  
M14 VCCINT  
M15 GND*  
M16 GND*  
M17 GND*  
M18 GND+  
M19 ^NCONFIG  
M20 state[2] LVTTL
M21 GND  
M22 VCCINT  
N1 GND*  
N2 GND*  
N3 GND*  
N4 GND+  
N5 GND*  
N6 GND*  
N7 GND*  
N8 GND_CKLK  
N9 VCCINT  
N10 GND  
N11 VCCIO  
N12 VCCINT  
N13 GND  
N14 VCCIO  
N15 C[6] LVTTL
N16 ACC[2] LVTTL
N17 C[2] LVTTL
N18 IR[1] LVTTL
N19 GND*  
N20 GND*  
N21 GND*  
N22 GND*  
P1 GND*  
P2 ACC[7] LVTTL
P3 GND*  
P4 GND*  
P5 GND*  
P6 GND*  
P7 GND*  
P8 VCCIO  
P9 GND  
P10 VCCINT  
P11 GND*  
P12 GND*  
P13 VCCIO  
P14 GND  
P15 VCCINT  
P16 OUT[1] LVTTL
P17 B[6] LVTTL
P18 A[4] LVTTL
P19 B[5] LVTTL
P20 GND*  
P21 GND*  
P22 GND*  
R1 C[7] LVTTL
R2 ACC[6] LVTTL
R3 GND*  
R4 GND*  
R5 GND*  
R6 GND+  
R7 VCCINT  
R8 GND  
R9 VCCIO  
R10 GND*  
R11 GND*  
R12 GND*  
R13 A[5] LVTTL
R14 VCCINT  
R15 GND  
R16 VCCIO  
R17 GND*  
R18 B[4] LVTTL
R19 ACC[1] LVTTL
R20 GND*  
R21 GND*  
R22 GND*  
T1 ACC[5] LVTTL
T2 GND*  
T3 GND*  
T4 GND_CLKOUT  
T5 VCC_CLKOUT  
T6 GND*  
T7 GND  
T8 VCCIO  
T9 GND*  
T10 GND*  
T11 GND*  
T12 GND*  
T13 GND*  
T14 GND*  
T15 VCCIO  
T16 GND  
T17 GND*  
T18 GND*  
T19 WR LVTTL
T20 B[3] LVTTL
T21 B[7] LVTTL
T22 GND*  
U1 GND*  
U2 GND*  
U3 ACC[4] LVTTL
U4 GND*  
U5 GND*  
U6 GND  
U7 GND*  
U8 GND*  
U9 GND*  
U10 GND*  
U11 GND*  
U12 GND*  
U13 GND*  
U14 GND*  
U15 OUT[7] LVTTL
U16 OUT[6] LVTTL
U17 GND  
U18 OUT[3] LVTTL
U19 state[1] LVTTL
U20 B[1] LVTTL
U21 C[0] LVTTL
U22 ACC[3] LVTTL
V1 GND*  
V2 GND*  
V3 GND*  
V4 GND*  
V5 GND*  
V6 GND*  
V7 GND*  
V8 GND*  
V9 GND*  
V10 GND*  
V11 GND+  
V12 GND+  
V13 A[3] LVTTL
V14 GND*  
V15 GND*  
V16 GND*  
V17 IR[4] LVTTL
V18 GND*  
V19 MARl LVTTL
V20 GND*  
V21 GND*  
V22 GND*  
W1 GND*  
W2 GND*  
W3 GND*  
W4 GND*  
W5 GND*  
W6 GND*  
W7 GND*  
W8 GND*  
W9 GND*  
W10 ^CONF_DONE  
W11 ^NSTATUS  
W12 #TCK  
W13 #TMS  
W14 GND*  
W15 OUT[2] LVTTL
W16 ZF LVTTL
W17 OUT[0] LVTTL
W18 OUT[4] LVTTL
W19 A[2] LVTTL
W20 B[0] LVTTL
W21 C[5] LVTTL
W22 GND*  
Y1 GND*  
Y2 GND*  
Y3 GND*  
Y4 GND*  
Y5 GND*  
Y6 GND*  
Y7 GND*  
Y8 GND*  
Y9 GND*  
Y10 res LVTTL
Y11 GND*  
Y12 IR[0] LVTTL
Y13 C[1] LVTTL
Y14 state[7] LVTTL
Y15 GND*  
Y16 A[7] LVTTL
Y17 GND*  
Y18 A[1] LVTTL
Y19 GND*  
Y20 C[4] LVTTL
Y21 GND*  
Y22 A[6] LVTTL
AA1 VCCINT  
AA2 GND  
AA3 GND*  
AA4 GND*  
AA5 GND*  
AA6 GND*  
AA7 GND*  
AA8 GND*  
AA9 GND*  
AA10 GND*  
AA11 GND*  
AA12 GND*  
AA13 IR[5] LVTTL
AA14 GND*  
AA15 GND*  
AA16 GND*  
AA17 C[3] LVTTL
AA18 IR[7] LVTTL
AA19 A[0] LVTTL
AA20 OUT[5] LVTTL
AA21 GND  
AA22 VCCINT  
AB1 GND  
AB2 GND*  
AB3 GND*  
AB4 GND*  
AB5 GND*  
AB6 GND*  
AB7 GND*  
AB8 GND*  
AB9 N.C.  
AB10 N.C.  
AB11 GND  
AB12 N.C.  
AB13 N.C.  
AB14 N.C.  
AB15 GND*  
AB16 GND*  
AB17 GND*  
AB18 RD LVTTL
AB19 GND*  
AB20 IR[3] LVTTL
AB21 state[5] LVTTL
AB22 GND  

[Top][Table of Contents]

Control Signals
Name Pin # Fan-Out Usage Global Usage
counter8:c1|SY_JKFF:u7|Q~reg0 LC6_15_N1 94 Clock Internal
cu:CU|MARl~reg0 LC6_11_Q2 12 Clock enable Non-global
cu:CU|OUTo~reg0 LC7_14_Q2 10 Output enable Non-global
cu:CU|CFl~reg0 LC1_13_R2 2 Clock enable Non-global
cu:CU|ZFl~reg0 LC4_10_O2 2 Clock enable Non-global
cu:CU|RD~reg0 LC7_16_O1 19 Output enable Internal
cu:CU|WR~reg0 LC6_9_P2 18 Write enable / Clock enable Internal
res Y10 40 Clock enable Non-global
CLKa L6 8 Clock Pin
ru:RU|A~435 LC6_13_U2 8 Output enable Non-global

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Global & Other Fast Signals
Name Pin # Fan-Out Global
counter8:c1|SY_JKFF:u7|Q~reg0 LC6_15_N1 94 yes
cu:CU|RD~reg0 LC7_16_O1 19 yes
cu:CU|WR~reg0 LC6_9_P2 18 yes
CLKa L6 8 yes

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Logical Memories
Name ESBs
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|content EC1_1_S2, EC2_1_S2, EC8_1_S2, EC7_1_S2, EC3_1_S2, EC6_1_S2, EC4_1_S2, EC5_1_S2

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Carry Chains
Carry Chain Length Number of Carry Chains
0 0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 12

[Top][Table of Contents]

Cascade Chains
Length Count
2 30
3 1

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Embedded Cells
Cell # Name Mode Turbo
EC1_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7] RAM On
EC2_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6] RAM On
EC8_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5] RAM On
EC7_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1] RAM On
EC3_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0] RAM On
EC6_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2] RAM On
EC4_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3] RAM On
EC5_1_S2 mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4] RAM On

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Non-Global High Fan-Out Signals
Name Fan-Out
cu:CU|ALUc[4]~reg0 88
cu:CU|ALUc[1]~reg0 61
cu:CU|state[0]~reg0 57
cu:CU|IR[3]~reg0 42
res 40
cu:CU|ALUc[0]~reg0 37
cu:CU|ALUc[3]~reg0 33
cu:CU|state[4]~reg0 31
cu:CU|IR[7]~reg0 31
cu:CU|ALUc[2]~reg0 30
cu:CU|91~38 26
cu:CU|406~8 25
cu:CU|IR[6]~reg0 25
eu:EU|1250~5 24
ru:RU|A~517 23
cu:CU|state[1]~reg0 23
ru:RU|A~520 22
ru:RU|A~521 21
ru:RU|A~524 21
ru:RU|A~522 21
ru:RU|A~518 21
ru:RU|A~523 21
ru:RU|A~519 20
cu:CU|state[3]~reg0 20
cu:CU|499~48 20
cu:CU|25~41 19
cu:CU|IR[2]~reg0 19
eu:EU|1252~15 19
cu:CU|IR[1]~reg0 18
cu:CU|IR[0]~reg0 17
cu:CU|91~8 16
eu:EU|1262~5 15
eu:EU|1265~5 15
eu:EU|1252~20 15
cu:CU|state[2]~reg0 14
eu:EU|CF 14
cu:CU|IR[5]~reg0 14
cu:CU|119~39 14
eu:EU|1268~14 13
mu:MU|1409~25 12
mu:MU|1409~20 12
mu:MU|1409~19 12
mu:MU|1409~21 12
mu:MU|1409~22 12
mu:MU|1409~18 12
cu:CU|ACCo~reg0 12
cu:CU|IR[4]~reg0 12
mu:MU|1409~24 12
eu:EU|1254~27 12
mu:MU|1409~23 12

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Peripheral Signals
Peripheral signal Source Usage Polarity
cu:CU|RD~reg0 LC7_16_O1 Output enable +ve
ru:RU|A~435 LC6_13_U2 Output enable +ve
cu:CU|OUTo~reg0 LC7_14_Q2 Output enable +ve

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Local Routing Interconnect
Local Routing Interconnects Number of MegaLABs
0 - 12 45
13 - 25 0
26 - 38 2
39 - 51 1
52 - 64 1
65 - 77 0
78 - 90 0
91 - 103 1
104 - 116 1
117 - 129 1

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MegaLAB Interconnect
MegaLAB Interconnects Number of MegaLABs
0 - 12 42
13 - 25 3
26 - 38 0
39 - 51 1
52 - 64 1
65 - 77 1
78 - 90 1
91 - 103 1
104 - 116 0
117 - 129 2

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LAB External Interconnect
LAB External Interconnects Number MegaLABs
0 - 22 44
23 - 45 1
46 - 68 1
69 - 91 0
92 - 114 2
115 - 137 1
138 - 160 0
161 - 183 0
184 - 206 0
207 - 229 3

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MegaLAB Usage Summary
MegaLAB Name Total Cells MegaLAB Interconnect Lines Column Fast Lines Driving In Column Fast Lines Driving Out Row Fast Lines Driving In Row Fast Lines Driving Out Fan-In Fan-Out Local Lines LAB External Interconnect Control Signals
A1 0 0 0 0 0 0 0 0 0 0 0
A2 0 0 0 0 0 0 0 0 0 0 0
B1 0 0 0 0 0 0 0 0 0 0 0
B2 0 0 0 0 0 0 0 0 0 0 0
C1 0 0 0 0 0 0 0 0 0 0 0
C2 0 0 0 0 0 0 0 0 0 0 0
D1 0 0 0 0 0 0 0 0 0 0 0
D2 0 0 0 0 0 0 0 0 0 0 0
E1 0 0 0 0 0 0 0 0 0 0 0
E2 0 0 0 0 0 0 0 0 0 0 0
F1 0 0 0 0 0 0 0 0 0 0 0
F2 0 0 0 0 0 0 0 0 0 0 0
G1 0 0 0 0 0 0 0 0 0 0 0
G2 0 0 0 0 0 0 0 0 0 0 0
H1 0 0 0 0 0 0 0 0 0 0 0
H2 0 0 0 0 0 0 0 0 0 0 0
I1 0 0 0 0 0 0 0 0 0 0 0
I2 0 0 0 0 0 0 0 0 0 0 0
J1 0 0 0 0 0 0 0 0 0 0 0
J2 0 0 0 0 0 0 0 0 0 0 0
K1 0 0 0 0 0 0 0 0 0 0 0
K2 0 0 0 0 0 0 0 0 0 0 0
L1 0 0 0 0 0 0 0 0 0 0 0
L2 0 0 0 0 0 0 0 0 0 0 0
M1 0 0 0 0 0 0 0 0 0 0 0
M2 0 0 0 0 0 0 4 0 0 0 0
N1 8 1 0 0 0 0 1 93 8 2 1
N2 0 3 2 0 0 0 4 0 0 3 0
O1 10 18 0 3 17 2 18 25 7 21 1
O2 160 98 43 46 4 12 49 223 126 221 2
P1 0 0 0 0 0 0 0 0 0 0 0
P2 10 18 16 5 0 0 22 27 9 20 1
Q1 0 0 0 0 0 0 0 0 0 0 0
Q2 81 64 41 39 3 0 48 145 60 112 2
R1 0 1 0 0 1 0 0 0 0 1 0
R2 87 81 57 37 2 0 69 126 50 127 2
S1 0 5 0 0 5 0 0 0 0 5 0
S2 135 126 77 29 2 2 80 175 96 214 5
T1 0 0 0 0 0 0 0 0 0 0 0
T2 0 4 4 0 0 0 3 0 0 4 0
U1 0 0 0 0 0 0 0 0 0 0 0
U2 153 117 64 49 1 0 65 279 112 217 2
V1 0 0 0 0 0 0 0 0 0 0 0
V2 1 3 3 1 0 0 7 1 0 4 0
W1 0 0 0 0 0 0 0 0 0 0 0
W2 20 21 20 10 1 0 25 20 11 24 0
X1 0 0 0 0 0 0 0 0 0 0 0
X2 41 50 41 16 1 0 43 136 28 57 3
Y1 0 0 0 0 0 0 0 0 0 0 0
Y2 1 4 3 1 1 0 5 1 0 4 2
Z1 0 0 0 0 0 0 0 0 0 0 0
Z2 63 69 60 26 1 0 56 62 35 103 1

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Row Interconnect
Row Lines Available Lines Used Half-Lines Used
A 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
B 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
C 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
D 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
E 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
F 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
G 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
H 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
I 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
J 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
K 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
L 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
M 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
N 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
O 100 20 / 100 ( 20 % ) 0 / 200 ( 0 % )
P 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
Q 100 3 / 100 ( 3 % ) 0 / 200 ( 0 % )
R 100 2 / 100 ( 2 % ) 0 / 200 ( 0 % )
S 100 7 / 100 ( 7 % ) 0 / 200 ( 0 % )
T 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
U 100 1 / 100 ( 1 % ) 0 / 200 ( 0 % )
V 100 0 / 100 ( 0 % ) 0 / 200 ( 0 % )
W 100 1 / 100 ( 1 % ) 0 / 200 ( 0 % )
X 100 1 / 100 ( 1 % ) 0 / 200 ( 0 % )
Y 100 1 / 100 ( 1 % ) 0 / 200 ( 0 % )
Z 100 1 / 100 ( 1 % ) 0 / 200 ( 0 % )
Total 2600 37 / 2600 ( 1 % ) 0 / 5200 ( 0 % )

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LAB Column Interconnect
MegaLAB Col. Col. Lines Available Lines Used Half-Lines Used
1 1 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 2 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 3 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 4 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 5 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 6 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 7 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 8 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 9 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 10 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 11 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 12 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 13 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 14 80 0 / 80 ( 0 % ) 1 / 160 ( < 1 % )
1 15 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
1 16 80 0 / 80 ( 0 % ) 1 / 160 ( < 1 % )
1 17 80 0 / 80 ( 0 % ) 2 / 160 ( 1 % )
2 1 80 0 / 80 ( 0 % ) 0 / 160 ( 0 % )
2 2 80 0 / 80 ( 0 % ) 5 / 160 ( 3 % )
2 3 80 0 / 80 ( 0 % ) 6 / 160 ( 3 % )
2 4 80 0 / 80 ( 0 % ) 7 / 160 ( 4 % )
2 5 80 0 / 80 ( 0 % ) 18 / 160 ( 11 % )
2 6 80 0 / 80 ( 0 % ) 20 / 160 ( 12 % )
2 7 80 0 / 80 ( 0 % ) 20 / 160 ( 12 % )
2 8 80 0 / 80 ( 0 % ) 26 / 160 ( 16 % )
2 9 80 0 / 80 ( 0 % ) 28 / 160 ( 17 % )
2 10 80 0 / 80 ( 0 % ) 28 / 160 ( 17 % )
2 11 80 0 / 80 ( 0 % ) 16 / 160 ( 10 % )
2 12 80 0 / 80 ( 0 % ) 24 / 160 ( 15 % )
2 13 80 0 / 80 ( 0 % ) 27 / 160 ( 16 % )
2 14 80 0 / 80 ( 0 % ) 17 / 160 ( 10 % )
2 15 80 0 / 80 ( 0 % ) 13 / 160 ( 8 % )
2 16 80 0 / 80 ( 0 % ) 4 / 160 ( 2 % )
2 17 80 0 / 80 ( 0 % ) 2 / 160 ( 1 % )
Total   2720 0 / 2720 ( 0 % ) 265 / 5440 ( 4 % )

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ESB Column Interconnect
Col. Lines Available Lines Used Half-Lines Used
0 128 0 / 128 ( 0 % ) 0 / 256 ( 0 % )
1 128 0 / 128 ( 0 % ) 3 / 256 ( 1 % )
Total 256 0 / 256 ( 0 % ) 3 / 512 ( < 1 % )

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Messages
Info: Found 0 design units and 0 entities in source file C:\minagawa\minicpu\mul.mif
Info: Found 0 design units and 0 entities in source file C:\minagawa\minicpu\test1.vwf
Info: Found 1 design units and 1 entities in source file C:\minagawa\minicpu\ram_8.v
   Info: Found entity 1: ram256x8
Info: Found 1 design units and 1 entities in source file C:\minagawa\minicpu\mu.v
   Info: Found entity 1: mu
Info: Found 1 design units and 1 entities in source file C:\minagawa\minicpu\ru.v
   Info: Found entity 1: ru
Info: Found 1 design units and 1 entities in source file C:\minagawa\minicpu\io.v
   Info: Found entity 1: io
Info: Found 1 design units and 1 entities in source file C:\minagawa\minicpu\eu.v
   Info: Found entity 1: eu
Info: Found 2 design units and 2 entities in source file C:\minagawa\minicpu\ck.v
   Info: Found entity 1: SY_JKFF
   Info: Found entity 2: counter8
Info: Found 1 design units and 1 entities in source file C:\minagawa\minicpu\cu.v
   Info: Found entity 1: cu
Info: Found 1 design units and 1 entities in source file C:\minagawa\minicpu\minicpu.v
   Info: Found entity 1: MINICPU
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_add_sub.tdf
   Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\altshift.tdf
   Info: Found entity 1: altshift
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\addcore.tdf
   Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\a_csnbuffer.tdf
   Info: Found entity 1: a_csnbuffer
Info: More than one TRI buffer drives output pin A- inferring tri-state bus
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_ram_dq.tdf
   Info: Found entity 1: lpm_ram_dq
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\altram.tdf
   Info: Found entity 1: altram
Warning: Can't feed logic gate io:IO|1~1 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~0 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~26 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~23 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~26 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~26 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~26 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|2 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~2 by tri-state signal
Warning: Cannot feed NOT gate CARRY_SUM eu:EU|lpm_add_sub:1304|addcore:adder|a_csnbuffer:result_node|sout[0] by tri-state signal
Warning: Cannot feed NOT gate CARRY_SUM eu:EU|lpm_add_sub:1308|addcore:adder|a_csnbuffer:result_node|sout[0] by tri-state signal
Warning: Cannot feed NOT gate CARRY_SUM eu:EU|lpm_add_sub:1312|addcore:adder|a_csnbuffer:result_node|sout[0] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1312|addcore:adder|a_csnbuffer:result_node|sout[0] of type CARRY_SUM by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|a_csnbuffer:result_node|sout[0] of type CARRY_SUM by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|a_csnbuffer:result_node|sout[0] of type CARRY_SUM by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|result_node$cin[0] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|result_node$cin[0] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|result_node$cin[0] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate io:IO|1~2 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~1 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|11~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|13~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|9~0 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|11~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|13~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|9~0 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|11~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|13~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|9~0 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|11~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|13~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|9~0 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|11~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|13~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|9~0 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|11~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|13~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|9~0 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|11~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|13~0 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|9~0 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~5 by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|unreg_res_node[1] of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1308|addcore:adder|unreg_res_node[1] by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|lpm_add_sub:1312|addcore:adder|14~0 by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1312|addcore:adder|unreg_res_node[1] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|14~0 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|result_node$cin[1] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate io:IO|1~3 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~9 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~9 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|11~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|13~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|9~1 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|11~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|13~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|9~1 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|11~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|13~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|9~1 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|11~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|13~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|9~1 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|11~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|13~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|9~1 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|11~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|13~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|9~1 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|11~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|13~1 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|9~1 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~8 by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|unreg_res_node[2] of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1308|addcore:adder|unreg_res_node[2] by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|lpm_add_sub:1312|addcore:adder|14~1 by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1312|addcore:adder|unreg_res_node[2] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|14~1 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|result_node$cin[2] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate io:IO|1~4 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~12 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~12 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~3 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~8 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|11~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|13~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|9~2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|11~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|13~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|9~2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|11~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|13~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|9~2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|11~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|13~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|9~2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|11~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|13~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|9~2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|11~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|13~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|9~2 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|11~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|13~2 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|9~2 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~11 by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|unreg_res_node[3] of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1308|addcore:adder|unreg_res_node[3] by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|lpm_add_sub:1312|addcore:adder|14~2 by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1312|addcore:adder|unreg_res_node[3] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|14~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|result_node$cin[3] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate io:IO|1~5 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~15 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~15 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~4 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~11 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|11~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|13~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|9~3 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|11~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|13~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|9~3 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|11~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|13~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|9~3 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|11~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|13~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|9~3 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|11~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|13~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|9~3 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|11~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|13~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|9~3 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|11~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|13~3 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|9~3 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~14 by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|unreg_res_node[4] of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1308|addcore:adder|unreg_res_node[4] by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|lpm_add_sub:1312|addcore:adder|14~3 by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1312|addcore:adder|unreg_res_node[4] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|14~3 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|result_node$cin[4] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate io:IO|1~6 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~18 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~18 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~5 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~14 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|11~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|13~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|9~4 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|11~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|13~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|9~4 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|11~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|13~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|9~4 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|11~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|13~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|9~4 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|11~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|13~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|9~4 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|11~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|13~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|9~4 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|11~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|13~4 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|9~4 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~17 by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|unreg_res_node[5] of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1308|addcore:adder|unreg_res_node[5] by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|lpm_add_sub:1312|addcore:adder|14~4 by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1312|addcore:adder|unreg_res_node[5] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|14~4 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|result_node$cin[5] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate io:IO|1~7 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~21 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~21 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~6 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~23 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~23 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~17 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~23 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|11~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|13~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|9~5 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|11~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|13~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|9~5 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|11~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|13~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|9~5 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|11~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|13~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|9~5 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|11~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|13~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|9~5 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|11~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|13~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|9~5 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|11~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|13~5 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|9~5 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~20 by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|unreg_res_node[6] of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1308|addcore:adder|unreg_res_node[6] by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|lpm_add_sub:1312|addcore:adder|14~5 by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1312|addcore:adder|unreg_res_node[6] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|14~5 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|result_node$cin[6] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate io:IO|1~8 of type IO_BUF (TRI) by tri-state signal
Warning: Can't feed logic gate eu:EU|1255~24 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1259~24 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1266~7 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1269~7 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1348~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1344~26 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1338~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~2 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1332~26 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1326~23 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1321~20 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1316~26 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1249~23 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|11~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|13~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1256|addcore:adder|9~6 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|11~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|13~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1260|addcore:adder|9~6 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|11~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|13~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1275|addcore:adder|9~6 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|11~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|13~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1281|addcore:adder|9~6 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|11~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|13~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1287|addcore:adder|9~6 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|11~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|13~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1293|addcore:adder|9~6 of type COMB (XOR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|11~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|13~6 of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1299|addcore:adder|9~6 of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|1313~23 by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|unreg_res_node[7] of type COMB (XOR) by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1308|addcore:adder|unreg_res_node[7] by tri-state signal
Warning: Cannot feed NOT gate COMB (AND) eu:EU|lpm_add_sub:1312|addcore:adder|14~6 by tri-state signal
Warning: Cannot feed NOT gate COMB (XOR) eu:EU|lpm_add_sub:1312|addcore:adder|unreg_res_node[7] by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1304|addcore:adder|14~6 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|lpm_add_sub:1308|addcore:adder|result_node$cin[7] of type COMB (OR) by tri-state signal
Warning: Can't feed logic gate eu:EU|1270~23 of type COMB (AND) by tri-state signal
Warning: Can't feed logic gate eu:EU|1261~23 of type COMB (AND) by tri-state signal
Warning: Converted TRI buffer to OR gate or removed OPNDRN
   Warning: Converting TRI node eu:EU|1355~9 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~1 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~2 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~3 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~4 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~5 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~6 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~7 that feeds logic to an OR gate
   Warning: Converting TRI node eu:EU|1355~8 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~10 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~11 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~12 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~13 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~14 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~15 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~16 that feeds logic to an OR gate
   Warning: Converting TRI node mu:MU|1409~17 that feeds logic to an OR gate
Info: Implemented 832 device resources
   Info: Implemented 2 input pins
   Info: Implemented 60 output pins
   Info: Implemented 762 logic cells
   Info: Implemented 8 RAM segments
Info: Selected device EP20K200EFC484-2X for design minicpu
Info: Started 1 fitting attempt on Mon Mar 04 2002 at 17:29:43
Warning: Found pins functioning as undefined clocks and/or memory enables
   Info: Assuming node CLKa is an undefined clock
Info: Clock CLKa has Internal fmax of 17.92 MHz between source register cu:CU|ACCo~reg0 and destination register eu:EU|ZF~reg0 (period= 55.79 ns)
   Info: + Longest register to register delay is 26.946 ns
      Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LC8_8_X2; REG Node = 'cu:CU|ACCo~reg0'
      Info: 2: + IC(2.649 ns) + CELL(0.779 ns) = 3.637 ns; Loc. = LC1_12_U2; COMB Node = 'ru:RU|A~447'
      Info: 3: + IC(0.000 ns) + CELL(0.689 ns) = 4.326 ns; Loc. = LC2_12_U2; COMB Node = 'ru:RU|A~522'
      Info: 4: + IC(2.567 ns) + CELL(1.139 ns) = 8.032 ns; Loc. = LC3_7_Z2; COMB Node = 'eu:EU|lpm_add_sub:1308|addcore:adder|a_csnbuffer:result_node|sout[2]'
      Info: 5: + IC(1.228 ns) + CELL(0.464 ns) = 9.724 ns; Loc. = LC4_5_Z2; COMB Node = 'eu:EU|1285~8677'
      Info: 6: + IC(2.567 ns) + CELL(1.034 ns) = 13.325 ns; Loc. = LC2_1_U2; COMB Node = 'eu:EU|1285~451'
      Info: 7: + IC(0.292 ns) + CELL(1.034 ns) = 14.651 ns; Loc. = LC3_1_U2; COMB Node = 'eu:EU|1285~462'
      Info: 8: + IC(0.292 ns) + CELL(1.034 ns) = 15.977 ns; Loc. = LC10_1_U2; COMB Node = 'eu:EU|1285~273'
      Info: 9: + IC(2.888 ns) + CELL(0.464 ns) = 19.329 ns; Loc. = LC9_15_S2; COMB Node = 'eu:EU|1257~257'
      Info: 10: + IC(0.292 ns) + CELL(0.464 ns) = 20.085 ns; Loc. = LC5_15_S2; COMB Node = 'eu:EU|1257~536'
      Info: 11: + IC(0.308 ns) + CELL(0.464 ns) = 20.857 ns; Loc. = LC1_15_S2; COMB Node = 'eu:EU|1257~492'
      Info: 12: + IC(0.340 ns) + CELL(0.464 ns) = 21.661 ns; Loc. = LC7_15_S2; COMB Node = 'eu:EU|1257~388'
      Info: 13: + IC(0.308 ns) + CELL(0.464 ns) = 22.433 ns; Loc. = LC2_15_S2; COMB Node = 'eu:EU|CONCATENATION~line~14[2]~239'
      Info: 14: + IC(0.351 ns) + CELL(0.464 ns) = 23.248 ns; Loc. = LC10_15_S2; COMB Node = 'eu:EU|CONCATENATION~line~14[2]~249'
      Info: 15: + IC(1.422 ns) + CELL(1.139 ns) = 25.809 ns; Loc. = LC2_4_S2; COMB Node = 'eu:EU|ZFo~103'
      Info: 16: + IC(0.348 ns) + CELL(0.789 ns) = 26.946 ns; Loc. = LC6_4_S2; REG Node = 'eu:EU|ZF~reg0'
   Info: - Smallest clock skew is -0.351 ns
      Info: + Shortest clock path from clock CLKa to destination register is 6.905 ns
         Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = Pin_L6; CLK Node = 'CLKa'
         Info: 2: + IC(1.360 ns) + CELL(0.643 ns) = 3.376 ns; Loc. = LC6_15_N1; REG Node = 'counter8:c1|SY_JKFF:u7|Q~reg0'
         Info: 3: + IC(3.529 ns) + CELL(0.000 ns) = 6.905 ns; Loc. = LC6_4_S2; REG Node = 'eu:EU|ZF~reg0'
      Info: - Longest clock path from clock CLKa to source register is 7.256 ns
         Info: 1: + IC(0.000 ns) + CELL(1.373 ns) = 1.373 ns; Loc. = Pin_L6; CLK Node = 'CLKa'
         Info: 2: + IC(1.360 ns) + CELL(0.643 ns) = 3.376 ns; Loc. = LC6_15_N1; REG Node = 'counter8:c1|SY_JKFF:u7|Q~reg0'
         Info: 3: + IC(3.880 ns) + CELL(0.000 ns) = 7.256 ns; Loc. = LC8_8_X2; REG Node = 'cu:CU|ACCo~reg0'
   Info: + Micro clock to output delay of source is 0.434 ns
   Info: + Micro setup delay of destination is 0.164 ns
   Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Design minicpu: Full compilation was successful. 0 errors, 345 warnings

[Top][Table of Contents]

Equations
Equations

[Top][Table of Contents]

Pin-Out File
Pin-Out File

[Top][Table of Contents]

Timing Settings
Assignment File Source Name Destination Name Option Setting
minicpu.psf     Include external delays to/from device pins in fmax calculations Off
minicpu.psf     RUN_ALL_TIMING_ANALYSES On
minicpu.psf     Ignore user-defined clock settings Off
minicpu.psf     Default hold multicycle Same As Multicycle
minicpu.psf     Cut off feedback from I/O pins On
minicpu.psf     Cut off clear and preset signal paths On
minicpu.psf     Cut off read during write signal paths On
minicpu.psf     Cut paths between unrelated clock domains On
minicpu.psf     Number of source nodes to report per destination node 10
minicpu.psf     Maximum Strongly Connected Component loop size 50

[Top][Table of Contents]

fmax (not incl. delays to/from pins)
Clock Name
   -- Destination Register Name
      -- Source Register Name
Required fmax Actual fmax (period)
CLKaNone17.92 MHz ( period = 55.790 ns )
   -- eu:EU|ZF~reg0None17.92 MHz ( period = 55.790 ns )
      -- cu:CU|ACCo~reg0None17.92 MHz ( period = 55.790 ns )
      -- cu:CU|PCo~reg0None18.23 MHz ( period = 54.852 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None18.31 MHz ( period = 54.614 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None18.31 MHz ( period = 54.614 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None18.31 MHz ( period = 54.614 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None18.31 MHz ( period = 54.614 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None18.31 MHz ( period = 54.614 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None18.31 MHz ( period = 54.614 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None18.31 MHz ( period = 54.614 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None18.31 MHz ( period = 54.614 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|PC[4]None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None18.48 MHz ( period = 54.104 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None18.95 MHz ( period = 52.760 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None18.95 MHz ( period = 52.760 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|SP[4]None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None18.49 MHz ( period = 54.092 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None18.96 MHz ( period = 52.748 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None18.96 MHz ( period = 52.748 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|SP[2]None18.59 MHz ( period = 53.806 ns )
      -- cu:CU|ACCo~reg0None18.59 MHz ( period = 53.806 ns )
      -- cu:CU|PCo~reg0None18.92 MHz ( period = 52.868 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None19.00 MHz ( period = 52.630 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None19.00 MHz ( period = 52.630 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None19.00 MHz ( period = 52.630 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None19.00 MHz ( period = 52.630 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None19.00 MHz ( period = 52.630 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None19.00 MHz ( period = 52.630 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None19.00 MHz ( period = 52.630 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None19.00 MHz ( period = 52.630 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|ACC[2]~reg0None18.59 MHz ( period = 53.804 ns )
      -- cu:CU|ACCo~reg0None18.59 MHz ( period = 53.804 ns )
      -- cu:CU|PCo~reg0None18.92 MHz ( period = 52.866 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None19.00 MHz ( period = 52.628 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None19.00 MHz ( period = 52.628 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None19.00 MHz ( period = 52.628 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None19.00 MHz ( period = 52.628 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None19.00 MHz ( period = 52.628 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None19.00 MHz ( period = 52.628 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None19.00 MHz ( period = 52.628 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None19.00 MHz ( period = 52.628 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|PC[2]None18.59 MHz ( period = 53.784 ns )
      -- cu:CU|ACCo~reg0None18.59 MHz ( period = 53.784 ns )
      -- cu:CU|PCo~reg0None18.92 MHz ( period = 52.846 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None19.01 MHz ( period = 52.608 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None19.01 MHz ( period = 52.608 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None19.01 MHz ( period = 52.608 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None19.01 MHz ( period = 52.608 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None19.01 MHz ( period = 52.608 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None19.01 MHz ( period = 52.608 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None19.01 MHz ( period = 52.608 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None19.01 MHz ( period = 52.608 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|PC[7]None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None18.77 MHz ( period = 53.286 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None19.25 MHz ( period = 51.942 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None19.25 MHz ( period = 51.942 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|PC[3]None18.77 MHz ( period = 53.264 ns )
      -- cu:CU|ACCo~reg0None18.77 MHz ( period = 53.264 ns )
      -- cu:CU|PCo~reg0None19.11 MHz ( period = 52.326 ns )
      -- cu:CU|SPo~reg0None19.43 MHz ( period = 51.478 ns )
      -- cu:CU|ALUc[3]~reg0None19.50 MHz ( period = 51.294 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None19.86 MHz ( period = 50.364 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None19.86 MHz ( period = 50.364 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None19.86 MHz ( period = 50.364 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None19.86 MHz ( period = 50.364 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None19.86 MHz ( period = 50.364 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None19.86 MHz ( period = 50.364 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|SP[7]None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None18.78 MHz ( period = 53.260 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None19.26 MHz ( period = 51.916 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None19.26 MHz ( period = 51.916 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- ru:RU|SP[6]None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra5None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra4None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra3None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra2None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra1None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra0None18.89 MHz ( period = 52.944 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra7None19.16 MHz ( period = 52.190 ns )
      -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra6None19.16 MHz ( period = 52.190 ns )
      -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)

[Top][Table of Contents]

Register-to-Register fmax
Source Register Name Destination Register Name Source Clock Name Destination Clock Name Required fmax Actual fmax (period)
cu:CU|ACCo~reg0 eu:EU|ZF~reg0 CLKa CLKa None 17.92 MHz ( period = 55.790 ns )
cu:CU|PCo~reg0 eu:EU|ZF~reg0 CLKa CLKa None 18.23 MHz ( period = 54.852 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0 eu:EU|ZF~reg0 CLKa CLKa None 18.31 MHz ( period = 54.614 ns )
Timing analysis restricted to 10 rows. To change the limit use Timing Settings (Project menu)        

[Top][Table of Contents]

tsu (Input Setup Times)
Data Pin Name
   -- Register Name
      -- Clock Name
Required tsu Actual tsu
resNone2.537 ns
   -- cu:CU|state[2]~reg0None2.537 ns
      -- CLKaNone2.537 ns
   -- cu:CU|state[0]~reg0None2.507 ns
      -- CLKaNone2.507 ns
   -- cu:CU|state[1]~reg0None2.435 ns
      -- CLKaNone2.435 ns
   -- cu:CU|state[3]~reg0None2.284 ns
      -- CLKaNone2.284 ns
   -- cu:CU|state[5]~reg0None2.267 ns
      -- CLKaNone2.267 ns
   -- cu:CU|state[7]~reg0None2.262 ns
      -- CLKaNone2.262 ns
   -- cu:CU|IR[6]~reg0None2.247 ns
      -- CLKaNone2.247 ns
   -- cu:CU|IR[5]~reg0None2.246 ns
      -- CLKaNone2.246 ns
   -- cu:CU|IR[2]~reg0None2.245 ns
      -- CLKaNone2.245 ns
   -- cu:CU|IR[4]~reg0None2.244 ns
      -- CLKaNone2.244 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)

[Top][Table of Contents]

th (Input Hold Times)
Data Pin Name
   -- Register Name
      -- Clock Name
Required th Actual th
resNone<= 0 ns
   -- ru:RU|PC[6]None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|ACC[3]~reg0None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|ACC[5]~reg0None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|ACC[1]~reg0None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|PC[0]None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|SP[0]None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|SP[5]None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|PC[5]None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|SP[3]None<= 0 ns
      -- CLKaNone<= 0 ns
   -- ru:RU|SP[1]None<= 0 ns
      -- CLKaNone<= 0 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)

[Top][Table of Contents]

tco (Clock to Output Delays)
Output Name
   -- Register Name
      -- Clock Name
Required tco Actual tco
C[6]None37.708 ns
   -- ru:RU|ACC[0]~reg0None37.708 ns
      -- CLKaNone37.708 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None37.004 ns
      -- CLKaNone37.004 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None37.004 ns
      -- CLKaNone37.004 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra5None37.004 ns
      -- CLKaNone37.004 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra4None37.004 ns
      -- CLKaNone37.004 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra3None37.004 ns
      -- CLKaNone37.004 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra2None37.004 ns
      -- CLKaNone37.004 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra1None37.004 ns
      -- CLKaNone37.004 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra0None37.004 ns
      -- CLKaNone37.004 ns
   -- ru:RU|SP[0]None36.700 ns
      -- CLKaNone36.700 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
C[7]None37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None37.267 ns
      -- CLKaNone37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None37.267 ns
      -- CLKaNone37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None37.267 ns
      -- CLKaNone37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None37.267 ns
      -- CLKaNone37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None37.267 ns
      -- CLKaNone37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None37.267 ns
      -- CLKaNone37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None37.267 ns
      -- CLKaNone37.267 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None37.267 ns
      -- CLKaNone37.267 ns
   -- ru:RU|ACC[0]~reg0None36.984 ns
      -- CLKaNone36.984 ns
   -- ru:RU|PC[6]None36.648 ns
      -- CLKaNone36.648 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
C[2]None36.448 ns
   -- ru:RU|ACC[0]~reg0None36.448 ns
      -- CLKaNone36.448 ns
   -- cu:CU|ACCo~reg0None36.245 ns
      -- CLKaNone36.245 ns
   -- cu:CU|PCo~reg0None35.776 ns
      -- CLKaNone35.776 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None35.657 ns
      -- CLKaNone35.657 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None35.657 ns
      -- CLKaNone35.657 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None35.657 ns
      -- CLKaNone35.657 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None35.657 ns
      -- CLKaNone35.657 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None35.657 ns
      -- CLKaNone35.657 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None35.657 ns
      -- CLKaNone35.657 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None35.657 ns
      -- CLKaNone35.657 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
C[4]None36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None36.111 ns
      -- CLKaNone36.111 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None35.439 ns
      -- CLKaNone35.439 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None35.439 ns
      -- CLKaNone35.439 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
C[1]None36.076 ns
   -- ru:RU|ACC[0]~reg0None36.076 ns
      -- CLKaNone36.076 ns
   -- ru:RU|SP[0]None35.068 ns
      -- CLKaNone35.068 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None34.897 ns
      -- CLKaNone34.897 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None34.897 ns
      -- CLKaNone34.897 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None34.897 ns
      -- CLKaNone34.897 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None34.897 ns
      -- CLKaNone34.897 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None34.897 ns
      -- CLKaNone34.897 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None34.897 ns
      -- CLKaNone34.897 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None34.897 ns
      -- CLKaNone34.897 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None34.897 ns
      -- CLKaNone34.897 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
C[5]None35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None35.821 ns
      -- CLKaNone35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None35.821 ns
      -- CLKaNone35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None35.821 ns
      -- CLKaNone35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None35.821 ns
      -- CLKaNone35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None35.821 ns
      -- CLKaNone35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None35.821 ns
      -- CLKaNone35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None35.821 ns
      -- CLKaNone35.821 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None35.821 ns
      -- CLKaNone35.821 ns
   -- cu:CU|ACCo~reg0None35.524 ns
      -- CLKaNone35.524 ns
   -- ru:RU|ACC[0]~reg0None35.504 ns
      -- CLKaNone35.504 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
C[3]None35.781 ns
   -- ru:RU|ACC[0]~reg0None35.781 ns
      -- CLKaNone35.781 ns
   -- cu:CU|ACCo~reg0None35.737 ns
      -- CLKaNone35.737 ns
   -- cu:CU|PCo~reg0None35.268 ns
      -- CLKaNone35.268 ns
   -- cu:CU|SPo~reg0None34.844 ns
      -- CLKaNone34.844 ns
   -- ru:RU|SP[0]None34.773 ns
      -- CLKaNone34.773 ns
   -- cu:CU|ALUc[3]~reg0None34.752 ns
      -- CLKaNone34.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None34.287 ns
      -- CLKaNone34.287 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None34.287 ns
      -- CLKaNone34.287 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None34.287 ns
      -- CLKaNone34.287 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None34.287 ns
      -- CLKaNone34.287 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
C[0]None35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra7None35.006 ns
      -- CLKaNone35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra6None35.006 ns
      -- CLKaNone35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra5None35.006 ns
      -- CLKaNone35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra4None35.006 ns
      -- CLKaNone35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra3None35.006 ns
      -- CLKaNone35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra2None35.006 ns
      -- CLKaNone35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra1None35.006 ns
      -- CLKaNone35.006 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra0None35.006 ns
      -- CLKaNone35.006 ns
   -- cu:CU|RD~reg0None34.684 ns
      -- CLKaNone34.684 ns
   -- ru:RU|ACC[0]~reg0None34.476 ns
      -- CLKaNone34.476 ns
   -- Timing analysis results restricted.To change the limit use Timing Settings (Project menu)
A[1]None19.552 ns
   -- cu:CU|PCo~reg0None19.552 ns
      -- CLKaNone19.552 ns
   -- cu:CU|ACCo~reg0None19.547 ns
      -- CLKaNone19.547 ns
   -- cu:CU|SPo~reg0None18.903 ns
      -- CLKaNone18.903 ns
   -- ru:RU|ACC[1]~reg0None15.001 ns
      -- CLKaNone15.001 ns
   -- ru:RU|SP[1]None14.881 ns
      -- CLKaNone14.881 ns
   -- ru:RU|PC[1]None14.455 ns
      -- CLKaNone14.455 ns
A[3]None19.552 ns
   -- cu:CU|PCo~reg0None19.552 ns
      -- CLKaNone19.552 ns
   -- cu:CU|ACCo~reg0None19.547 ns
      -- CLKaNone19.547 ns
   -- cu:CU|SPo~reg0None18.903 ns
      -- CLKaNone18.903 ns
   -- ru:RU|PC[3]None16.236 ns
      -- CLKaNone16.236 ns
   -- ru:RU|ACC[3]~reg0None15.058 ns
      -- CLKaNone15.058 ns
   -- ru:RU|SP[3]None14.930 ns
      -- CLKaNone14.930 ns
A[5]None19.552 ns
   -- cu:CU|PCo~reg0None19.552 ns
      -- CLKaNone19.552 ns
   -- cu:CU|ACCo~reg0None19.547 ns
      -- CLKaNone19.547 ns
   -- cu:CU|SPo~reg0None18.903 ns
      -- CLKaNone18.903 ns
   -- ru:RU|ACC[5]~reg0None14.969 ns
      -- CLKaNone14.969 ns
   -- ru:RU|SP[5]None14.849 ns
      -- CLKaNone14.849 ns
   -- ru:RU|PC[5]None14.391 ns
      -- CLKaNone14.391 ns
A[7]None19.552 ns
   -- cu:CU|PCo~reg0None19.552 ns
      -- CLKaNone19.552 ns
   -- cu:CU|ACCo~reg0None19.547 ns
      -- CLKaNone19.547 ns
   -- cu:CU|SPo~reg0None18.903 ns
      -- CLKaNone18.903 ns
   -- ru:RU|SP[7]None14.957 ns
      -- CLKaNone14.957 ns
   -- ru:RU|ACC[7]~reg0None14.911 ns
      -- CLKaNone14.911 ns
   -- ru:RU|PC[7]None14.508 ns
      -- CLKaNone14.508 ns
A[0]None18.210 ns
   -- cu:CU|PCo~reg0None18.210 ns
      -- CLKaNone18.210 ns
   -- cu:CU|ACCo~reg0None18.205 ns
      -- CLKaNone18.205 ns
   -- cu:CU|SPo~reg0None17.561 ns
      -- CLKaNone17.561 ns
   -- ru:RU|ACC[0]~reg0None16.858 ns
      -- CLKaNone16.858 ns
   -- ru:RU|SP[0]None15.850 ns
      -- CLKaNone15.850 ns
   -- ru:RU|PC[0]None15.344 ns
      -- CLKaNone15.344 ns
A[2]None18.210 ns
   -- cu:CU|PCo~reg0None18.210 ns
      -- CLKaNone18.210 ns
   -- cu:CU|ACCo~reg0None18.205 ns
      -- CLKaNone18.205 ns
   -- cu:CU|SPo~reg0None17.561 ns
      -- CLKaNone17.561 ns
   -- ru:RU|PC[2]None14.756 ns
      -- CLKaNone14.756 ns
   -- ru:RU|ACC[2]~reg0None14.742 ns
      -- CLKaNone14.742 ns
   -- ru:RU|SP[2]None14.323 ns
      -- CLKaNone14.323 ns
A[4]None18.210 ns
   -- cu:CU|PCo~reg0None18.210 ns
      -- CLKaNone18.210 ns
   -- cu:CU|ACCo~reg0None18.205 ns
      -- CLKaNone18.205 ns
   -- cu:CU|SPo~reg0None17.561 ns
      -- CLKaNone17.561 ns
   -- ru:RU|ACC[4]~reg0None17.168 ns
      -- CLKaNone17.168 ns
   -- ru:RU|PC[4]None14.870 ns
      -- CLKaNone14.870 ns
   -- ru:RU|SP[4]None14.354 ns
      -- CLKaNone14.354 ns
A[6]None18.210 ns
   -- cu:CU|PCo~reg0None18.210 ns
      -- CLKaNone18.210 ns
   -- cu:CU|ACCo~reg0None18.205 ns
      -- CLKaNone18.205 ns
   -- ru:RU|PC[6]None17.749 ns
      -- CLKaNone17.749 ns
   -- cu:CU|SPo~reg0None17.561 ns
      -- CLKaNone17.561 ns
   -- ru:RU|SP[6]None14.750 ns
      -- CLKaNone14.750 ns
   -- ru:RU|ACC[6]~reg0None14.323 ns
      -- CLKaNone14.323 ns
OUT[6]None18.115 ns
   -- ru:RU|PC[6]None18.115 ns
      -- CLKaNone18.115 ns
   -- cu:CU|PCo~reg0None17.723 ns
      -- CLKaNone17.723 ns
   -- cu:CU|SPo~reg0None17.155 ns
      -- CLKaNone17.155 ns
   -- cu:CU|ACCo~reg0None16.735 ns
      -- CLKaNone16.735 ns
   -- cu:CU|OUTo~reg0None15.131 ns
      -- CLKaNone15.131 ns
   -- ru:RU|SP[6]None15.116 ns
      -- CLKaNone15.116 ns
   -- ru:RU|ACC[6]~reg0None14.689 ns
      -- CLKaNone14.689 ns
OUT[4]None17.368 ns
   -- cu:CU|ACCo~reg0None17.368 ns
      -- CLKaNone17.368 ns
   -- ru:RU|ACC[4]~reg0None17.234 ns
      -- CLKaNone17.234 ns
   -- cu:CU|PCo~reg0None16.865 ns
      -- CLKaNone16.865 ns
   -- cu:CU|SPo~reg0None16.490 ns
      -- CLKaNone16.490 ns
   -- cu:CU|OUTo~reg0None15.131 ns
      -- CLKaNone15.131 ns
   -- ru:RU|PC[4]None14.936 ns
      -- CLKaNone14.936 ns
   -- ru:RU|SP[4]None14.420 ns
      -- CLKaNone14.420 ns
OUT[7]None17.275 ns
   -- cu:CU|ACCo~reg0None17.275 ns
      -- CLKaNone17.275 ns
   -- cu:CU|SPo~reg0None16.652 ns
      -- CLKaNone16.652 ns
   -- cu:CU|PCo~reg0None16.200 ns
      -- CLKaNone16.200 ns
   -- cu:CU|OUTo~reg0None15.131 ns
      -- CLKaNone15.131 ns
   -- ru:RU|SP[7]None14.826 ns
      -- CLKaNone14.826 ns
   -- ru:RU|ACC[7]~reg0None14.780 ns
      -- CLKaNone14.780 ns
   -- ru:RU|PC[7]None14.377 ns
      -- CLKaNone14.377 ns
OUT[2]None17.234 ns
   -- cu:CU|ACCo~reg0None17.234 ns
      -- CLKaNone17.234 ns
   -- cu:CU|PCo~reg0None16.765 ns
      -- CLKaNone16.765 ns
   -- cu:CU|SPo~reg0None16.341 ns
      -- CLKaNone16.341 ns
   -- cu:CU|OUTo~reg0None15.131 ns
      -- CLKaNone15.131 ns
   -- ru:RU|PC[2]None14.775 ns
      -- CLKaNone14.775 ns
   -- ru:RU|ACC[2]~reg0None14.761 ns
      -- CLKaNone14.761 ns
   -- ru:RU|SP[2]None14.342 ns
      -- CLKaNone14.342 ns
OUT[0]None16.899 ns
   -- ru:RU|ACC[0]~reg0None16.899 ns
      -- CLKaNone16.899 ns
   -- ru:RU|SP[0]None15.891 ns
      -- CLKaNone15.891 ns
   -- ru:RU|PC[0]None15.385 ns
      -- CLKaNone15.385 ns
   -- cu:CU|OUTo~reg0None15.131 ns
      -- CLKaNone15.131 ns
   -- cu:CU|ACCo~reg0None14.976 ns
      -- CLKaNone14.976 ns
   -- cu:CU|SPo~reg0None14.327 ns
      -- CLKaNone14.327 ns
   -- cu:CU|PCo~reg0None13.858 ns
      -- CLKaNone13.858 ns
OUT[3]None16.204 ns
   -- ru:RU|PC[3]None16.204 ns
      -- CLKaNone16.204 ns
   -- cu:CU|OUTo~reg0None15.131 ns
      -- CLKaNone15.131 ns
   -- ru:RU|ACC[3]~reg0None15.026 ns
      -- CLKaNone15.026 ns
   -- cu:CU|ACCo~reg0None15.017 ns
      -- CLKaNone15.017 ns
   -- ru:RU|SP[3]None14.898 ns
      -- CLKaNone14.898 ns
   -- cu:CU|SPo~reg0None14.368 ns
      -- CLKaNone14.368 ns
   -- cu:CU|PCo~reg0None13.899 ns
      -- CLKaNone13.899 ns
B[0]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra7None14.763 ns
      -- CLKaNone14.763 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra6None14.763 ns
      -- CLKaNone14.763 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra5None14.763 ns
      -- CLKaNone14.763 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra4None14.763 ns
      -- CLKaNone14.763 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra3None14.763 ns
      -- CLKaNone14.763 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra2None14.763 ns
      -- CLKaNone14.763 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra1None14.763 ns
      -- CLKaNone14.763 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[0]~reg_ra0None14.763 ns
      -- CLKaNone14.763 ns
B[1]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra7None15.825 ns
      -- CLKaNone15.825 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra6None15.825 ns
      -- CLKaNone15.825 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra5None15.825 ns
      -- CLKaNone15.825 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra4None15.825 ns
      -- CLKaNone15.825 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra3None15.825 ns
      -- CLKaNone15.825 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra2None15.825 ns
      -- CLKaNone15.825 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra1None15.825 ns
      -- CLKaNone15.825 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[1]~reg_ra0None15.825 ns
      -- CLKaNone15.825 ns
B[2]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra7None15.861 ns
      -- CLKaNone15.861 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra6None15.861 ns
      -- CLKaNone15.861 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra5None15.861 ns
      -- CLKaNone15.861 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra4None15.861 ns
      -- CLKaNone15.861 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra3None15.861 ns
      -- CLKaNone15.861 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra2None15.861 ns
      -- CLKaNone15.861 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra1None15.861 ns
      -- CLKaNone15.861 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[2]~reg_ra0None15.861 ns
      -- CLKaNone15.861 ns
B[3]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra7None15.799 ns
      -- CLKaNone15.799 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra6None15.799 ns
      -- CLKaNone15.799 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra5None15.799 ns
      -- CLKaNone15.799 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra4None15.799 ns
      -- CLKaNone15.799 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra3None15.799 ns
      -- CLKaNone15.799 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra2None15.799 ns
      -- CLKaNone15.799 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra1None15.799 ns
      -- CLKaNone15.799 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[3]~reg_ra0None15.799 ns
      -- CLKaNone15.799 ns
B[4]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra7None14.788 ns
      -- CLKaNone14.788 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra6None14.788 ns
      -- CLKaNone14.788 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra5None14.788 ns
      -- CLKaNone14.788 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra4None14.788 ns
      -- CLKaNone14.788 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra3None14.788 ns
      -- CLKaNone14.788 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra2None14.788 ns
      -- CLKaNone14.788 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra1None14.788 ns
      -- CLKaNone14.788 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[4]~reg_ra0None14.788 ns
      -- CLKaNone14.788 ns
B[5]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra7None15.826 ns
      -- CLKaNone15.826 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra6None15.826 ns
      -- CLKaNone15.826 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra5None15.826 ns
      -- CLKaNone15.826 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra4None15.826 ns
      -- CLKaNone15.826 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra3None15.826 ns
      -- CLKaNone15.826 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra2None15.826 ns
      -- CLKaNone15.826 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra1None15.826 ns
      -- CLKaNone15.826 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[5]~reg_ra0None15.826 ns
      -- CLKaNone15.826 ns
B[6]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra7None14.752 ns
      -- CLKaNone14.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra6None14.752 ns
      -- CLKaNone14.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra5None14.752 ns
      -- CLKaNone14.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra4None14.752 ns
      -- CLKaNone14.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra3None14.752 ns
      -- CLKaNone14.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra2None14.752 ns
      -- CLKaNone14.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra1None14.752 ns
      -- CLKaNone14.752 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[6]~reg_ra0None14.752 ns
      -- CLKaNone14.752 ns
B[7]None15.982 ns
   -- cu:CU|RD~reg0None15.982 ns
      -- CLKaNone15.982 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra7None15.834 ns
      -- CLKaNone15.834 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra6None15.834 ns
      -- CLKaNone15.834 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra5None15.834 ns
      -- CLKaNone15.834 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra4None15.834 ns
      -- CLKaNone15.834 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra3None15.834 ns
      -- CLKaNone15.834 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra2None15.834 ns
      -- CLKaNone15.834 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra1None15.834 ns
      -- CLKaNone15.834 ns
   -- mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|q[7]~reg_ra0None15.834 ns
      -- CLKaNone15.834 ns
OUT[1]None15.150 ns
   -- cu:CU|SPo~reg0None15.150 ns
      -- CLKaNone15.150 ns
   -- ru:RU|ACC[1]~reg0None15.140 ns
      -- CLKaNone15.140 ns
   -- ru:RU|SP[1]None15.020 ns
      -- CLKaNone15.020 ns
   -- ru:RU|PC[1]None14.594 ns
      -- CLKaNone14.594 ns
   -- cu:CU|ACCo~reg0None14.479 ns
      -- CLKaNone14.479 ns
   -- cu:CU|PCo~reg0None14.021 ns
      -- CLKaNone14.021 ns
   -- cu:CU|OUTo~reg0None13.789 ns
      -- CLKaNone13.789 ns
OUT[5]None14.902 ns
   -- ru:RU|ACC[5]~reg0None14.902 ns
      -- CLKaNone14.902 ns
   -- cu:CU|ACCo~reg0None14.839 ns
      -- CLKaNone14.839 ns
   -- ru:RU|SP[5]None14.782 ns
      -- CLKaNone14.782 ns
   -- ru:RU|PC[5]None14.324 ns
      -- CLKaNone14.324 ns
   -- cu:CU|SPo~reg0None14.179 ns
      -- CLKaNone14.179 ns
   -- cu:CU|OUTo~reg0None13.789 ns
      -- CLKaNone13.789 ns
   -- cu:CU|PCo~reg0None13.753 ns
      -- CLKaNone13.753 ns
ACC[5]None14.724 ns
   -- ru:RU|ACC[5]~reg0None14.724 ns
      -- CLKaNone14.724 ns
ACC[7]None14.429 ns
   -- ru:RU|ACC[7]~reg0None14.429 ns
      -- CLKaNone14.429 ns
ACC[0]None14.199 ns
   -- ru:RU|ACC[0]~reg0None14.199 ns
      -- CLKaNone14.199 ns
ACC[6]None14.167 ns
   -- ru:RU|ACC[6]~reg0None14.167 ns
      -- CLKaNone14.167 ns
RDNone13.849 ns
   -- cu:CU|RD~reg0None13.849 ns
      -- CLKaNone13.849 ns
ACC[4]None13.362 ns
   -- ru:RU|ACC[4]~reg0None13.362 ns
      -- CLKaNone13.362 ns
ACC[3]None13.133 ns
   -- ru:RU|ACC[3]~reg0None13.133 ns
      -- CLKaNone13.133 ns
ACC[1]None13.117 ns
   -- ru:RU|ACC[1]~reg0None13.117 ns
      -- CLKaNone13.117 ns
IR[1]None12.985 ns
   -- cu:CU|IR[1]~reg0None12.985 ns
      -- CLKaNone12.985 ns
ACC[2]None12.945 ns
   -- ru:RU|ACC[2]~reg0None12.945 ns
      -- CLKaNone12.945 ns
IR[3]None12.864 ns
   -- cu:CU|IR[3]~reg0None12.864 ns
      -- CLKaNone12.864 ns
ZFNone12.788 ns
   -- eu:EU|ZF~reg0None12.788 ns
      -- CLKaNone12.788 ns
IR[7]None12.749 ns
   -- cu:CU|IR[7]~reg0None12.749 ns
      -- CLKaNone12.749 ns
IR[4]None12.712 ns
   -- cu:CU|IR[4]~reg0None12.712 ns
      -- CLKaNone12.712 ns
state[5]None12.685 ns
   -- cu:CU|state[5]~reg0None12.685 ns
      -- CLKaNone12.685 ns
IR[0]None12.653 ns
   -- cu:CU|IR[0]~reg0None12.653 ns
      -- CLKaNone12.653 ns
state[7]None12.648 ns
   -- cu:CU|state[7]~reg0None12.648 ns
      -- CLKaNone12.648 ns
IR[5]None12.611 ns
   -- cu:CU|IR[5]~reg0None12.611 ns
      -- CLKaNone12.611 ns
MARlNone12.610 ns
   -- cu:CU|MARl~reg0None12.610 ns
      -- CLKaNone12.610 ns
WRNone12.517 ns
   -- cu:CU|WR~reg0None12.517 ns
      -- CLKaNone12.517 ns
state[1]None12.428 ns
   -- cu:CU|state[1]~reg0None12.428 ns
      -- CLKaNone12.428 ns
IR[2]None12.374 ns
   -- cu:CU|IR[2]~reg0None12.374 ns
      -- CLKaNone12.374 ns
state[3]None12.314 ns
   -- cu:CU|state[3]~reg0None12.314 ns
      -- CLKaNone12.314 ns
state[0]None12.298 ns
   -- cu:CU|state[0]~reg0None12.298 ns
      -- CLKaNone12.298 ns
IR[6]None12.232 ns
   -- cu:CU|IR[6]~reg0None12.232 ns
      -- CLKaNone12.232 ns
state[4]None11.382 ns
   -- cu:CU|state[4]~reg0None11.382 ns
      -- CLKaNone11.382 ns
state[6]None11.248 ns
   -- cu:CU|state[6]~reg0None11.248 ns
      -- CLKaNone11.248 ns
state[2]None10.124 ns
   -- cu:CU|state[2]~reg0None10.124 ns
      -- CLKaNone10.124 ns

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Processing Time
Module Name Elapsed Time
Database Builder 00:00:05
Logic Synthesizer 00:01:34
Fitter 00:01:08
Assembler 00:00:03
Delay Annotator 00:00:03
Timing Analyzer 00:00:01
Total 00:02:56

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