minicpu - Quartus II Simulation Report File


Report Information
ProjectC:\minagawa\minicpu\db\minicpu.quartus_db
Simulator Settingsminicpu
Quartus II Version1.1 Build 155 07/18/2001


Table of Contents
    Simulator Report
        Legal Notice
        Project Settings
            General Settings
        Results for "minicpu" Simulator Settings
            Summary
            Simulator Settings
            Simulation Waveforms
            Logical Memories
                |MINICPU|mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|content
            Messages
            Processing Time


Legal Notice

Copyright (C) 1991-2001 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein.

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General Settings
Option Setting
Start date & time 03/04/2002 17:14:50
Main task Simulation
Settings name minicpu
Simulation mode Timing
Compiler Settings minicpu

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Summary
Option Setting
Simulation Start Time 0 ps
Simulation End Time 1.0 ms
Simulation Coverage 89 %
Number of transitions 390225

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Simulator Settings
Option Setting
Simulation mode Timing
Simulator settings name minicpu
Start time 0ns
Vector input source C:\minagawa\minicpu\test1.vwf
Check outputs Off
Detect glitches Off
Glitch interval 1ns
Report simulation coverage On
Add pins automatically to simulation output waveforms On
Estimate power consumption Off
Detect setup and hold time violations Off

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Simulation Waveforms
Waveform report data cannot be output to HTML.
Please use Quartus II to view the waveform report data.

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|MINICPU|mu:MU|ram256x8:ram|lpm_ram_dq:inst_1|altram:sram|content
Memory report data cannot be output to HTML.
Please use Quartus II to view the memory report data.

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Messages
Info: Design minicpu: Simulation was successful. 0 errors, 0 warnings

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Processing Time
Module Name Elapsed Time
Netlist Builder 00:00:01
Simulator 00:00:20

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